;********************************************************************************************************
;                                               INIT
;
; File      : OS_CPU_A.s
; Version   : V2.84
; Port By   : zhangchao
;
; For       : ARMv7M Cortex-M3
; Mode      : Thumb2
; Toolchain : ARMCC
;********************************************************************************************************

                EXPORT  SYS_INIT
                                                                               
LPC_SC_SCS        EQU  0x400FC1A0    ;;_WDWORD(0x400FC1A0, 0x00000020);       // LPC_SC->SCS       = SCS_Val;                                                                                                     
LPC_SC_CLKSRCSEL  EQU  0x400FC10C    ;;_WDWORD(0x400FC10C, 0x1);       // LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/ 
LPC_SC_PLL0CFG    EQU  0x400FC084    ;;_WDWORD(0x400FC084, 0x00000009);       // LPC_SC->PLL0CFG   = PLL0CFG_Val;                                              
LPC_SC_PLL0CON    EQU  0x400FC080    ;;_WDWORD(0x400FC080, 0x1);       // LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */       
LPC_SC_PLL0FEED   EQU  0x400FC08C    ;;_WDWORD(0x400FC08C, 0xAA);       // LPC_SC->PLL0FEED  = 0xAA;                                                           
                                     ;;_WDWORD(0x400FC08C, 0x55);       // LPC_SC->PLL0FEED  = 0x55;                                                           
                                     ;;_sleep_ (10);                                                                                                           
                                     ;;                                                                                                                        
LPC_SC_PLL1CFG    EQU  0x400FC0A4    ;;_WDWORD(0x400FC0A4, 0x00000023);       // LPC_SC->PLL1CFG   = PLL1CFG_Val;                                              
LPC_SC_PLL1CON    EQU  0x400FC0A0    ;;_WDWORD(0x400FC0A0, 0x1);       // LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */       
LPC_SC_PLL1FEED   EQU  0x400FC0AC    ;;_WDWORD(0x400FC0AC, 0xAA);       // LPC_SC->PLL1FEED  = 0xAA;                                                           
                                     ;;_WDWORD(0x400FC0AC, 0x55);       // LPC_SC->PLL1FEED  = 0x55;                                                           
                                     ;;_sleep_ (10);                                                                                                           
                                     ;;                                                                                                                        
LPC_SC_CCLKSEL    EQU  0x400FC104    ;;_WDWORD(0x400FC104, 0x101);       // LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */     
LPC_SC_USBCLKSEL  EQU  0x400FC108    ;;_WDWORD(0x400FC108, 0x201);       // LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */     
LPC_SC_EMCCLKSEL  EQU  0x400FC100    ;;_WDWORD(0x400FC100, 0x1);       // LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */       
LPC_SC_PCLKSEL    EQU  0x400FC1A8    ;;_WDWORD(0x400FC1A8, 0x2);       // LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */       
LPC_SC_PCONP      EQU  0x400FC04C    ;;_WDWORD(0x400FC04C, 0x042887DE);       // LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
LPC_SC_CLKOUTCFG  EQU  0x400FC1C8    ;;_WDWORD(0x400FC1C8, 0x00000100);       // LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
                                     ;;_sleep_ (10);                                                                                                           
                                     ;;                                                                                                                        
LPC_IOCON_P2_16   EQU  0x4002C140    ;;_WDWORD(0x4002C140, 0x21);       // LPC_IOCON->P2_16 = 0x21;                                                            
LPC_IOCON_P2_17   EQU  0x4002C144  	 ;;_WDWORD(0x4002C144, 0x21);       // LPC_IOCON->P2_17 = 0x21;                                                            
LPC_IOCON_P2_18   EQU  0x4002C148  	 ;;_WDWORD(0x4002C148, 0x21);       // LPC_IOCON->P2_18 = 0x21;                                                            
LPC_IOCON_P2_20   EQU  0x4002C150  	 ;;_WDWORD(0x4002C150, 0x21);       // LPC_IOCON->P2_20 = 0x21;                                                            
LPC_IOCON_P2_24   EQU  0x4002C160  	 ;;_WDWORD(0x4002C160, 0x21);       // LPC_IOCON->P2_24 = 0x21;                                                            
LPC_IOCON_P2_28   EQU  0x4002C170  	 ;;_WDWORD(0x4002C170, 0x21);       // LPC_IOCON->P2_28 = 0x21;                                                            
LPC_IOCON_P2_29   EQU  0x4002C174  	 ;;_WDWORD(0x4002C174, 0x21);       // LPC_IOCON->P2_29 = 0x21;                                                            
LPC_IOCON_P2_30   EQU  0x4002C178  	 ;;_WDWORD(0x4002C178, 0x21);       // LPC_IOCON->P2_30 = 0x21;                                                            
LPC_IOCON_P2_31   EQU  0x4002C17C  	 ;;_WDWORD(0x4002C17C, 0x21);       // LPC_IOCON->P2_31 = 0x21;                                                            
LPC_IOCON_P3_0    EQU  0x4002C180  	 ;;_WDWORD(0x4002C180, 0x21);       // LPC_IOCON->P3_0 = 0x21;                                                             
LPC_IOCON_P3_1    EQU  0x4002C184  	 ;;_WDWORD(0x4002C184, 0x21);       // LPC_IOCON->P3_1 = 0x21;                                                             
LPC_IOCON_P3_2    EQU  0x4002C188  	 ;;_WDWORD(0x4002C188, 0x21);       // LPC_IOCON->P3_2 = 0x21;                                                             
LPC_IOCON_P3_3    EQU  0x4002C18C  	 ;;_WDWORD(0x4002C18C, 0x21);       // LPC_IOCON->P3_3 = 0x21;                                                             
LPC_IOCON_P3_4    EQU  0x4002C190  	 ;;_WDWORD(0x4002C190, 0x21);       // LPC_IOCON->P3_4 = 0x21;                                                             
LPC_IOCON_P3_5    EQU  0x4002C194  	 ;;_WDWORD(0x4002C194, 0x21);       // LPC_IOCON->P3_5 = 0x21;                                                             
LPC_IOCON_P3_6    EQU  0x4002C198  	 ;;_WDWORD(0x4002C198, 0x21);       // LPC_IOCON->P3_6 = 0x21;                                                             
LPC_IOCON_P3_7    EQU  0x4002C19C  	 ;;_WDWORD(0x4002C19C, 0x21);       // LPC_IOCON->P3_7 = 0x21;                                                             
LPC_IOCON_P3_8    EQU  0x4002C1A0  	 ;;_WDWORD(0x4002C1A0, 0x21);       // LPC_IOCON->P3_8 = 0x21;                                                             
LPC_IOCON_P3_9    EQU  0x4002C1A4  	 ;;_WDWORD(0x4002C1A4, 0x21);       // LPC_IOCON->P3_9 = 0x21;                                                             
LPC_IOCON_P3_10   EQU  0x4002C1A8  	 ;;_WDWORD(0x4002C1A8, 0x21);       // LPC_IOCON->P3_10 = 0x21;                                                            
LPC_IOCON_P3_11   EQU  0x4002C1AC  	 ;;_WDWORD(0x4002C1AC, 0x21);       // LPC_IOCON->P3_11 = 0x21;                                                            
LPC_IOCON_P3_12   EQU  0x4002C1B0  	 ;;_WDWORD(0x4002C1B0, 0x21);       // LPC_IOCON->P3_12 = 0x21;                                                            
LPC_IOCON_P3_13   EQU  0x4002C1B4  	 ;;_WDWORD(0x4002C1B4, 0x21);       // LPC_IOCON->P3_13 = 0x21;                                                            
LPC_IOCON_P3_14   EQU  0x4002C1B8  	 ;;_WDWORD(0x4002C1B8, 0x21);       // LPC_IOCON->P3_14 = 0x21;                                                            
LPC_IOCON_P3_15   EQU  0x4002C1BC  	 ;;_WDWORD(0x4002C1BC, 0x21);       // LPC_IOCON->P3_15 = 0x21;                                                            
LPC_IOCON_P3_16   EQU  0x4002C1C0  	 ;;_WDWORD(0x4002C1C0, 0x21);       // LPC_IOCON->P3_16 = 0x21;                                                            
LPC_IOCON_P3_17   EQU  0x4002C1C4  	 ;;_WDWORD(0x4002C1C4, 0x21);       // LPC_IOCON->P3_17 = 0x21;                                                            
LPC_IOCON_P3_18   EQU  0x4002C1C8  	 ;;_WDWORD(0x4002C1C8, 0x21);       // LPC_IOCON->P3_18 = 0x21;                                                            
LPC_IOCON_P3_19   EQU  0x4002C1CC  	 ;;_WDWORD(0x4002C1CC, 0x21);       // LPC_IOCON->P3_19 = 0x21;                                                            
LPC_IOCON_P3_20   EQU  0x4002C1D0  	 ;;_WDWORD(0x4002C1D0, 0x21);       // LPC_IOCON->P3_20 = 0x21;                                                            
LPC_IOCON_P3_21   EQU  0x4002C1D4  	 ;;_WDWORD(0x4002C1D4, 0x21);       // LPC_IOCON->P3_21 = 0x21;                                                            
LPC_IOCON_P3_22   EQU  0x4002C1D8  	 ;;_WDWORD(0x4002C1D8, 0x21);       // LPC_IOCON->P3_22 = 0x21;                                                            
LPC_IOCON_P3_23   EQU  0x4002C1DC  	 ;;_WDWORD(0x4002C1DC, 0x21);       // LPC_IOCON->P3_23 = 0x21;                                                            
LPC_IOCON_P3_24   EQU  0x4002C1E0  	 ;;_WDWORD(0x4002C1E0, 0x21);       // LPC_IOCON->P3_24 = 0x21;                                                            
LPC_IOCON_P3_25   EQU  0x4002C1E4  	 ;;_WDWORD(0x4002C1E4, 0x21);       // LPC_IOCON->P3_25 = 0x21;                                                            
LPC_IOCON_P3_26   EQU  0x4002C1E8  	 ;;_WDWORD(0x4002C1E8, 0x21);       // LPC_IOCON->P3_26 = 0x21;                                                            
LPC_IOCON_P3_27   EQU  0x4002C1EC  	 ;;_WDWORD(0x4002C1EC, 0x21);       // LPC_IOCON->P3_27 = 0x21;                                                            
LPC_IOCON_P3_28   EQU  0x4002C1F0  	 ;;_WDWORD(0x4002C1F0, 0x21);       // LPC_IOCON->P3_28 = 0x21;                                                            
LPC_IOCON_P3_29   EQU  0x4002C1F4  	 ;;_WDWORD(0x4002C1F4, 0x21);       // LPC_IOCON->P3_29 = 0x21;                                                            
LPC_IOCON_P3_30   EQU  0x4002C1F8  	 ;;_WDWORD(0x4002C1F8, 0x21);       // LPC_IOCON->P3_30 = 0x21;                                                            
LPC_IOCON_P3_31   EQU  0x4002C1FC  	 ;;_WDWORD(0x4002C1FC, 0x21);       // LPC_IOCON->P3_31 = 0x21;                                                            
LPC_IOCON_P4_0    EQU  0x4002C200  	 ;;_WDWORD(0x4002C200, 0x21);       // LPC_IOCON->P4_0 = 0x21;                                                             
LPC_IOCON_P4_1    EQU  0x4002C204  	 ;;_WDWORD(0x4002C204, 0x21);       // LPC_IOCON->P4_1 = 0x21;                                                             
LPC_IOCON_P4_2    EQU  0x4002C208  	 ;;_WDWORD(0x4002C208, 0x21);       // LPC_IOCON->P4_2 = 0x21;                                                             
LPC_IOCON_P4_3    EQU  0x4002C20C  	 ;;_WDWORD(0x4002C20C, 0x21);       // LPC_IOCON->P4_3 = 0x21;                                                             
LPC_IOCON_P4_4    EQU  0x4002C210  	 ;;_WDWORD(0x4002C210, 0x21);       // LPC_IOCON->P4_4 = 0x21;                                                             
LPC_IOCON_P4_5    EQU  0x4002C214  	 ;;_WDWORD(0x4002C214, 0x21);       // LPC_IOCON->P4_5 = 0x21;                                                             
LPC_IOCON_P4_6    EQU  0x4002C218  	 ;;_WDWORD(0x4002C218, 0x21);       // LPC_IOCON->P4_6 = 0x21;                                                             
LPC_IOCON_P4_7    EQU  0x4002C21C  	 ;;_WDWORD(0x4002C21C, 0x21);       // LPC_IOCON->P4_7 = 0x21;                                                             
LPC_IOCON_P4_8    EQU  0x4002C220  	 ;;_WDWORD(0x4002C220, 0x21);       // LPC_IOCON->P4_8 = 0x21;                                                             
LPC_IOCON_P4_9    EQU  0x4002C224  	 ;;_WDWORD(0x4002C224, 0x21);       // LPC_IOCON->P4_9 = 0x21;                                                             
LPC_IOCON_P4_10   EQU  0x4002C228  	 ;;_WDWORD(0x4002C228, 0x21);       // LPC_IOCON->P4_10 = 0x21;                                                            
LPC_IOCON_P4_11   EQU  0x4002C22C  	 ;;_WDWORD(0x4002C22C, 0x21);       // LPC_IOCON->P4_11 = 0x21;                                                            
LPC_IOCON_P4_12   EQU  0x4002C230  	 ;;_WDWORD(0x4002C230, 0x21);       // LPC_IOCON->P4_12 = 0x21;                                                            
LPC_IOCON_P4_13   EQU  0x4002C234  	 ;;_WDWORD(0x4002C234, 0x21);       // LPC_IOCON->P4_13 = 0x21;                                                            
LPC_IOCON_P4_14   EQU  0x4002C238  	 ;;_WDWORD(0x4002C238, 0x21);       // LPC_IOCON->P4_14 = 0x21;                                                            
LPC_IOCON_P4_25   EQU  0x4002C264  	 ;;_WDWORD(0x4002C264, 0x21);       // LPC_IOCON->P4_25 = 0x21;                                                            
                                     ;;                                                                                                                        
                                     ;;_WDWORD(0x400FC0C4, 0x04288FDE);       // LPC_SC->PCONP   	|= 0x00000800; //RESET VALUE IS 0x0408829E                  
                                     ;;// Init SDRAM controller                                                                                                
LPC_SC_EMCDLYCTL  EQU  0x400FC1DC  	 ;;_WDWORD(0x400FC1DC, 0x80A18);       // LPC_SC->EMCDLYCTL |= (8<<0); //RESET VALUE IS 0x210                              
                                   	 ;;// Set data read delay                                                                                                  
                                   	 ;;// LPC_SC->EMCDLYCTL |=(8<<8);                                                                                          
                                   	 ;;// LPC_SC->EMCDLYCTL |= (0x08 <<16);                                                                                    

LPC_EMC_Control   EQU  0x2009C000  	          ;;_WDWORD(0x2009C000, 0x1);       // LPC_EMC->Control =1;                                                                 
LPC_EMC_DynamicReadConfig   EQU   0x2009C028 	;;_WDWORD(0x2009C028, 0x1);       // LPC_EMC->DynamicReadConfig = 1;                                                      
LPC_EMC_DynamicRasCas0      EQU   0x2009C104	;;_WDWORD(0x2009C104, 0x0);       // LPC_EMC->DynamicRasCas0 = 0;                                                         
                                              ;;_WDWORD(0x2009C104, 0x303);       // LPC_EMC->DynamicRasCas0 |=(3<<8);                                                  
                                              ;;// LPC_EMC->DynamicRasCas0 |= (3<<0);                                                                                   

LPC_EMC_DynamicRP     EQU     0x2009C030    	;;_WDWORD(0x2009C030, 0x2);       // LPC_EMC->DynamicRP   P2C(SDRAM_TRP);                                                 
LPC_EMC_DynamicRAS    EQU     0x2009C034    	;;_WDWORD(0x2009C034, 0x3);       // LPC_EMC->DynamicRAS = P2C(SDRAM_TRAS);                                               
LPC_EMC_DynamicSREX   EQU     0x2009C038    	;;_WDWORD(0x2009C038, 0x5);       // LPC_EMC->DynamicSREX = P2C(SDRAM_TXSR);                                              
LPC_EMC_DynamicAPR    EQU     0x2009C03C    	;;_WDWORD(0x2009C03C, 0x1);       // LPC_EMC->DynamicAPR = SDRAM_TAPR;                                                    
LPC_EMC_DynamicDAL    EQU     0x2009C040    	;;_WDWORD(0x2009C040, 0x5);       // LPC_EMC->DynamicDAL = SDRAM_TDAL+P2C(SDRAM_TRP);                                     
LPC_EMC_DynamicWR     EQU     0x2009C044    	;;_WDWORD(0x2009C044, 0x3);       // LPC_EMC->DynamicWR   SDRAM_TWR;                                                      
LPC_EMC_DynamicRC     EQU     0x2009C048    	;;_WDWORD(0x2009C048, 0x4);       // LPC_EMC->DynamicRC   P2C(SDRAM_TRC);                                                 
LPC_EMC_DynamicRFC    EQU     0x2009C04C    	;;_WDWORD(0x2009C04C, 0x4);       // LPC_EMC->DynamicRFC = P2C(SDRAM_TRFC);                                               
LPC_EMC_DynamicXSR    EQU     0x2009C050    	;;_WDWORD(0x2009C050, 0x5);       // LPC_EMC->DynamicXSR = P2C(SDRAM_TXSR);                                               
LPC_EMC_DynamicRRD    EQU     0x2009C054    	;;_WDWORD(0x2009C054, 0x1);       // LPC_EMC->DynamicRRD = P2C(SDRAM_TRRD);                                               
LPC_EMC_DynamicMRD    EQU     0x2009C058    	;;_WDWORD(0x2009C058, 0x3);       // LPC_EMC->DynamicMRD = SDRAM_TMRD;                                                    

                                              ;;// 13 row, 9 - col, SDRAM                                                                                               
LPC_EMC_DynamicConfig0   EQU  0x2009C100  	  ;;_WDWORD(0x2009C100, 0x0004680);       // LPC_EMC->DynamicConfig0 = 0x0004680;                                           
                                           	  ;;// JEDEC General SDRAM Initialization Sequence                                                                          
                                           	  ;;// DELAY to allow power and clocks to stabilize ~100 us                                                                 
                                           	  ;;// NOP                                                                                                                  
LPC_EMC_DynamicControl   EQU  0x2009C020  	  ;;_WDWORD(0x2009C020, 0x0183);       // LPC_EMC->DynamicControl = 0x0183;                                                 
                                              ;;_sleep_ (10);       // for(i= 200*30; i;i--);                                                                           
                                                                                                               
                                              ;;_WDWORD(0x2009C020, 0x0103);       // LPC_EMC->DynamicControl = 0x0103;                                                 
LPC_EMC_DynamicRefresh   EQU  0x2009C024  	  ;;_WDWORD(0x2009C024, 0x2);       // LPC_EMC->DynamicRefresh = 2;                                                         
                                              ;;_sleep_ (10);       // for(i= 256; i; --i); // > 128 clk                                                                
                                              ;;_WDWORD(0x2009C024, 0x1D);       // LPC_EMC->DynamicRefresh = P2C(SDRAM_REFRESH) >> 4;                                  
                                              
                                              ;;_WDWORD(0x2009C020, 0x00000083);       //   LPC_EMC->DynamicControl    = 0x00000083; /* Issue MODE command */           
                                              ;;_RDWORD(0xA0064000); // Dummy = *((volatile uint32_t *)(SDRAM_BASE_ADDR | (0x32<<13)));                                 
                                              ;;// NORM                                                                                                                 
                                              ;;_WDWORD(0x2009C020, 0x0);       // LPC_EMC->DynamicControl = 0x0000;                                                    
                                          	  ;;_WDWORD(0x2009C100, 0x84680);       // LPC_EMC->DynamicConfig0 |=(1<<19);                                               
                                              ;;_sleep_ (10);       // for(i = 100000; i;i--);	                                                                        



		PRESERVE8
		AREA   |.text|, CODE, READONLY

SYS_INIT
        LDR     R0, =LPC_SC_SCS                         ;;_WDWORD(0x400FC1A0, 0x00000020);       // LPC_SC->SCS       = SCS_Val; 
        LDR     R1, =0x20                               ;;_WDWORD(0x400FC10C, 0x1);       // LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;  
        STR     R1, [R0]                                ;;_WDWORD(0x400FC084, 0x00000009);       // LPC_SC->PLL0CFG   = PLL0CFG_ 
        LDR     R0, =LPC_SC_CLKSRCSEL                   ;;_WDWORD(0x400FC080, 0x1);       // LPC_SC->PLL0CON   = 0x01;           
        LDR     R1, =0x1                                ;;_WDWORD(0x400FC08C, 0xAA);       // LPC_SC->PLL0FEED  = 0xAA;          
        STR     R1, [R0]                                ;;_WDWORD(0x400FC08C, 0x55);       // LPC_SC->PLL0FEED  = 0x55;          
        LDR     R0, =LPC_SC_PLL0CFG                     ;;_sleep_ (10);                                                          
        LDR     R1, =0x9
        STR     R1, [R0]
        LDR     R0, =LPC_SC_PLL0CON                                                                                            
        LDR     R1, =0x1
        STR     R1, [R0]
        LDR     R0, =LPC_SC_PLL0FEED                    
        LDR     R1, =0xAA
        STR     R1, [R0]
        LDR     R1, =0x55
        STR     R1, [R0]
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
                                                        ;;_WDWORD(0x400FC0A4, 0x00000023);       // LPC_SC->PLL1CFG   = PLL1CFG_ 
        LDR     R0, =LPC_SC_PLL1CFG                     ;;_WDWORD(0x400FC0A0, 0x1);       // LPC_SC->PLL1CON   = 0x01;           
        LDR     R1, =0x23
        STR     R1, [R0]
        LDR     R0, =LPC_SC_PLL1CON                     ;;_WDWORD(0x400FC0AC, 0xAA);       // LPC_SC->PLL1FEED  = 0xAA;          
        LDR     R1, =0x1
        STR     R1, [R0]
        LDR     R0, =LPC_SC_PLL1FEED                    ;;_WDWORD(0x400FC0AC, 0x55);       // LPC_SC->PLL1FEED  = 0x55;          
        LDR     R1, =0xAA
        STR     R1, [R0]
        LDR     R1, =0x55
        STR     R1, [R0]
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        
        LDR     R0, =LPC_SC_CCLKSEL                     ;;_sleep_ (10);                                                          
        LDR     R1, =0x101
        STR     R1, [R0]
        LDR     R0, =LPC_SC_USBCLKSEL                   ;;                                                                       
        LDR     R1, =0x201
        STR     R1, [R0]
        LDR     R0, =LPC_SC_EMCCLKSEL                   ;;_WDWORD(0x400FC104, 0x101);       // LPC_SC->CCLKSEL   = CCLKSEL_Val;  
        LDR     R1, =0x1
        STR     R1, [R0]
        LDR     R0, =LPC_SC_PCLKSEL                     ;;_WDWORD(0x400FC108, 0x201);       // LPC_SC->USBCLKSEL = USBCLKSEL_Val 
        LDR     R1, =0x2
        STR     R1, [R0]
        LDR     R0, =LPC_SC_PCONP                       ;;_WDWORD(0x400FC100, 0x1);       // LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;  
        LDR     R1, =0x042887DE
        STR     R1, [R0]
        LDR     R0, =LPC_SC_CLKOUTCFG                   ;;_WDWORD(0x400FC1A8, 0x2);       // LPC_SC->PCLKSEL   = PCLKSEL_Val;    
        LDR     R1, =0x100
        STR     R1, [R0]
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        
        LDR     R0, =LPC_IOCON_P2_16                    ;;_WDWORD(0x400FC04C, 0x042887DE);       // LPC_SC->PCONP     = PCONP_Va 
        LDR     R1, =0x21
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P2_17                    ;;_WDWORD(0x400FC1C8, 0x00000100);       // LPC_SC->CLKOUTCFG = CLKOUTCF 
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P2_18                    ;;_sleep_ (10);                                                          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P2_20                    ;;                                                                       
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P2_24                    ;;_WDWORD(0x4002C140, 0x21);       // LPC_IOCON->P2_16 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P2_28                  	 ;;_WDWORD(0x4002C144, 0x21);       // LPC_IOCON->P2_17 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P2_29                  	 ;;_WDWORD(0x4002C148, 0x21);       // LPC_IOCON->P2_18 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P2_30                  	 ;;_WDWORD(0x4002C150, 0x21);       // LPC_IOCON->P2_20 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P2_31                  	 ;;_WDWORD(0x4002C160, 0x21);       // LPC_IOCON->P2_24 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_0                   	 ;;_WDWORD(0x4002C170, 0x21);       // LPC_IOCON->P2_28 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_1                   	 ;;_WDWORD(0x4002C174, 0x21);       // LPC_IOCON->P2_29 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_2                   	 ;;_WDWORD(0x4002C178, 0x21);       // LPC_IOCON->P2_30 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_3                   	 ;;_WDWORD(0x4002C17C, 0x21);       // LPC_IOCON->P2_31 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_4                   	 ;;_WDWORD(0x4002C180, 0x21);       // LPC_IOCON->P3_0 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_5                   	 ;;_WDWORD(0x4002C184, 0x21);       // LPC_IOCON->P3_1 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_6                   	 ;;_WDWORD(0x4002C188, 0x21);       // LPC_IOCON->P3_2 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_7                   	 ;;_WDWORD(0x4002C18C, 0x21);       // LPC_IOCON->P3_3 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_8                   	 ;;_WDWORD(0x4002C190, 0x21);       // LPC_IOCON->P3_4 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_9                   	 ;;_WDWORD(0x4002C194, 0x21);       // LPC_IOCON->P3_5 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_10                  	 ;;_WDWORD(0x4002C198, 0x21);       // LPC_IOCON->P3_6 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_11                  	 ;;_WDWORD(0x4002C19C, 0x21);       // LPC_IOCON->P3_7 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_12                  	 ;;_WDWORD(0x4002C1A0, 0x21);       // LPC_IOCON->P3_8 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_13                  	 ;;_WDWORD(0x4002C1A4, 0x21);       // LPC_IOCON->P3_9 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_14                  	 ;;_WDWORD(0x4002C1A8, 0x21);       // LPC_IOCON->P3_10 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_15                  	 ;;_WDWORD(0x4002C1AC, 0x21);       // LPC_IOCON->P3_11 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_16                  	 ;;_WDWORD(0x4002C1B0, 0x21);       // LPC_IOCON->P3_12 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_17                  	 ;;_WDWORD(0x4002C1B4, 0x21);       // LPC_IOCON->P3_13 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_18                  	 ;;_WDWORD(0x4002C1B8, 0x21);       // LPC_IOCON->P3_14 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_19                  	 ;;_WDWORD(0x4002C1BC, 0x21);       // LPC_IOCON->P3_15 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_20                  	 ;;_WDWORD(0x4002C1C0, 0x21);       // LPC_IOCON->P3_16 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_21                  	 ;;_WDWORD(0x4002C1C4, 0x21);       // LPC_IOCON->P3_17 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_22                  	 ;;_WDWORD(0x4002C1C8, 0x21);       // LPC_IOCON->P3_18 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_23                  	 ;;_WDWORD(0x4002C1CC, 0x21);       // LPC_IOCON->P3_19 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_24                  	 ;;_WDWORD(0x4002C1D0, 0x21);       // LPC_IOCON->P3_20 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_25                  	 ;;_WDWORD(0x4002C1D4, 0x21);       // LPC_IOCON->P3_21 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_26                  	 ;;_WDWORD(0x4002C1D8, 0x21);       // LPC_IOCON->P3_22 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_27                  	 ;;_WDWORD(0x4002C1DC, 0x21);       // LPC_IOCON->P3_23 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_28                  	 ;;_WDWORD(0x4002C1E0, 0x21);       // LPC_IOCON->P3_24 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_29                  	 ;;_WDWORD(0x4002C1E4, 0x21);       // LPC_IOCON->P3_25 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_30                  	 ;;_WDWORD(0x4002C1E8, 0x21);       // LPC_IOCON->P3_26 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P3_31                  	 ;;_WDWORD(0x4002C1EC, 0x21);       // LPC_IOCON->P3_27 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_0                   	 ;;_WDWORD(0x4002C1F0, 0x21);       // LPC_IOCON->P3_28 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_1                   	 ;;_WDWORD(0x4002C1F4, 0x21);       // LPC_IOCON->P3_29 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_2                   	 ;;_WDWORD(0x4002C1F8, 0x21);       // LPC_IOCON->P3_30 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_3                   	 ;;_WDWORD(0x4002C1FC, 0x21);       // LPC_IOCON->P3_31 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_4                   	 ;;_WDWORD(0x4002C200, 0x21);       // LPC_IOCON->P4_0 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_5                   	 ;;_WDWORD(0x4002C204, 0x21);       // LPC_IOCON->P4_1 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_6                   	 ;;_WDWORD(0x4002C208, 0x21);       // LPC_IOCON->P4_2 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_7                   	 ;;_WDWORD(0x4002C20C, 0x21);       // LPC_IOCON->P4_3 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_8                   	 ;;_WDWORD(0x4002C210, 0x21);       // LPC_IOCON->P4_4 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_9                   	 ;;_WDWORD(0x4002C214, 0x21);       // LPC_IOCON->P4_5 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_10                  	 ;;_WDWORD(0x4002C218, 0x21);       // LPC_IOCON->P4_6 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_11                  	 ;;_WDWORD(0x4002C21C, 0x21);       // LPC_IOCON->P4_7 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_12                  	 ;;_WDWORD(0x4002C220, 0x21);       // LPC_IOCON->P4_8 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_13                  	 ;;_WDWORD(0x4002C224, 0x21);       // LPC_IOCON->P4_9 = 0x21;           
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_14                  	 ;;_WDWORD(0x4002C228, 0x21);       // LPC_IOCON->P4_10 = 0x21;          
        STR     R1, [R0]
        LDR     R0, =LPC_IOCON_P4_25                  	 ;;_WDWORD(0x4002C22C, 0x21);       // LPC_IOCON->P4_11 = 0x21;          
        STR     R1, [R0]
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        
        LDR     R0, =LPC_SC_PCONP                       ;;// Init SDRAM controller
        LDR     R1, =0x04288FDE
        STR     R1, [R0]
        LDR     R0, =LPC_SC_EMCDLYCTL                 	;;_WDWORD(0x400FC0C4, 0x04288FDE);       // LPC_SC->PCONP   	|= 0x00000800; //RESET VALUE IS 0x0408829E 
        LDR     R1, =0x80A18
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_Control
        LDR     R1, =0x1
        STR     R1, [R0]                  	                                                                               
        LDR     R0, =LPC_EMC_DynamicReadConfig        	;;_WDWORD(0x400FC1DC, 0x80A18);       // LPC_SC->EMCDLYCTL |= (8<<0); //RESET VALUE IS 0x210             
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_DynamicRasCas0           	;;// Set data read delay                                                                                 
        LDR     R1, =0x0
        STR     R1, [R0]
        LDR     R1, =0x303
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_DynamicRP                  ;;// LPC_SC->EMCDLYCTL |=(8<<8);                                                                         
        LDR     R1, =0x2
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_DynamicRAS                 ;;// LPC_SC->EMCDLYCTL |= (0x08 <<16);                                                                   
        LDR     R1, =0x3
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_DynamicSREX                
        LDR     R1, =0x5
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_DynamicAPR               	
        LDR     R1, =0x1
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_DynamicDAL
        LDR     R1, =0x5
        STR     R1, [R0]               	
        LDR     R0, =LPC_EMC_DynamicWR
        LDR     R1, =0x3
        STR     R1, [R0]                	
        LDR     R0, =LPC_EMC_DynamicRC
        LDR     R1, =0x4
        STR     R1, [R0]                	
        LDR     R0, =LPC_EMC_DynamicRFC
        STR     R1, [R0] 
        LDR     R0, =LPC_EMC_DynamicXSR
        LDR     R1, =0x5
        STR     R1, [R0] 
        LDR     R0, =LPC_EMC_DynamicRRD
        LDR     R1, =0x1
        STR     R1, [R0] 
        LDR     R0, =LPC_EMC_DynamicMRD
        LDR     R1, =0x3
        STR     R1, [R0]
        
         
        LDR     R0, =LPC_EMC_DynamicConfig0
        LDR     R1, =0x4680
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_DynamicControl
        LDR     R1, =0x183
        STR     R1, [R0]
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        
        LDR     R1, =0x103
        STR     R1, [R0]
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
               
        LDR     R0, =LPC_EMC_DynamicRefresh
        LDR     R1, =0x2
        STR     R1, [R0]     
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP

        LDR     R1, =0x1D
        STR     R1, [R0]

        LDR     R0, =LPC_EMC_DynamicControl
        LDR     R1, =0x83
        STR     R1, [R0]
        
        LDR     R1, =0xA0064000
        LDR     R0, [R1]       

        LDR     R0, =LPC_EMC_DynamicControl
        LDR     R1, =0x0
        STR     R1, [R0]
        LDR     R0, =LPC_EMC_DynamicConfig0
        LDR     R1, =0x84680
        STR     R1, [R0]
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        NOP
        
		BX      LR
		NOP

       ;;_WDWORD(0x2009C000, 0x1);       // LPC_EMC->Control =1;                   
       ;;_WDWORD(0x2009C028, 0x1);       // LPC_EMC->DynamicReadConfig = 1;        
       ;;_WDWORD(0x2009C104, 0x0);       // LPC_EMC->DynamicRasCas0 = 0;           
       ;;_WDWORD(0x2009C104, 0x303);       // LPC_EMC->DynamicRasCas0 |=(3<<8);    
       ;;// LPC_EMC->DynamicRasCas0 |= (3<<0);                                     
                                                                                   
       ;;_WDWORD(0x2009C030, 0x2);       // LPC_EMC->DynamicRP   P2C(SDRAM_TRP);              
       ;;_WDWORD(0x2009C034, 0x3);       // LPC_EMC->DynamicRAS = P2C(SDRAM_TRAS);            
       ;;_WDWORD(0x2009C038, 0x5);       // LPC_EMC->DynamicSREX = P2C(SDRAM_TXSR);           
       ;;_WDWORD(0x2009C03C, 0x1);       // LPC_EMC->DynamicAPR = SDRAM_TAPR;                 
       ;;_WDWORD(0x2009C040, 0x5);       // LPC_EMC->DynamicDAL = SDRAM_TDAL+P2C(SDRAM_TRP);  
       ;;_WDWORD(0x2009C044, 0x3);       // LPC_EMC->DynamicWR   SDRAM_TWR;                   
       ;;_WDWORD(0x2009C048, 0x4);       // LPC_EMC->DynamicRC   P2C(SDRAM_TRC);              
       ;;_WDWORD(0x2009C04C, 0x4);       // LPC_EMC->DynamicRFC = P2C(SDRAM_TRFC);            
       ;;_WDWORD(0x2009C050, 0x5);       // LPC_EMC->DynamicXSR = P2C(SDRAM_TXSR);            
       ;;_WDWORD(0x2009C054, 0x1);       // LPC_EMC->DynamicRRD = P2C(SDRAM_TRRD);            
       ;;_WDWORD(0x2009C058, 0x3);       // LPC_EMC->DynamicMRD = SDRAM_TMRD;                 
                                                                                   
       ;;// 13 row, 9 - col, SDRAM                                                 
       ;;_WDWORD(0x2009C100, 0x0004680);       // LPC_EMC->DynamicConfig0 = 0x00046
       ;;// JEDEC General SDRAM Initialization Sequence                            
       ;;// DELAY to allow power and clocks to stabilize ~100 us                   
       ;;// NOP                                                                    
       ;;_WDWORD(0x2009C020, 0x0183);       // LPC_EMC->DynamicControl = 0x0183;   
       ;;_sleep_ (10);       // for(i= 200*30; i;i--);                             
                                                                                   
       ;;_WDWORD(0x2009C020, 0x0103);       // LPC_EMC->DynamicControl = 0x0103;   
       ;;_WDWORD(0x2009C024, 0x2);       // LPC_EMC->DynamicRefresh = 2;           
       ;;_sleep_ (10);       // for(i= 256; i; --i); // > 128 clk                  
       ;;_WDWORD(0x2009C024, 0x1D);       // LPC_EMC->DynamicRefresh = P2C(SDRAM_RE
                                                                                   
       ;;_WDWORD(0x2009C020, 0x00000083);       //   LPC_EMC->DynamicControl    = 0
       ;;_RDWORD(0xA0064000); // Dummy = *((volatile uint32_t *)(SDRAM_BASE_ADDR | 
       ;;// NORM                                                                   
       ;;_WDWORD(0x2009C020, 0x0);       // LPC_EMC->DynamicControl = 0x0000;      
       ;;_WDWORD(0x2009C100, 0x84680);       // LPC_EMC->DynamicConfig0 |=(1<<19); 
        
        
		ALIGN
        END
